Crisis financieras y el papel de la banca central : un enfoque teórico

Las crisis financieras tienen efectos nefastos en una economía en caso que ésta no pueda ser prevenida eficientemente por el planificador central o el agente regulador de este sector. En el manejo de las crisis es importante distinguir entre la regulación previa que se tiene que dar al sector financiero y el comportamiento de la autoridad monetaria en caso que se produzca la crisis a pesar de la regulación. Para poder ofrecer soluciones en cuanto a regulación y comportamiento de la banca central es preciso conocer cómo se manejan las instituciones financieras en su afán de conseguir captaciones y colocar las mismas para obtener utilidades; así mismo es importante conocer el comportamiento de los agregados en caso que se produzca un shock monetario que pueda llevar a la economía a una crisis bancaria, en este contexto las soluciones propuestas dependerán de las preferencias por estabilidad de determinados agregados por parte de la autoridad. No es posible entender el comportamiento de las instituciones financieras y del gobierno como ente regulador si no se considera a estos como agentes racionales que maximizan su utilidad, en este trabajo se presenta estas características y se plantea diferentes situaciones para ofrecer recomendaciones que sean compatibles con los incentivos de cada agente participante en una situación de crisis bancaria

Three-dimensional Reconstruction of the Caspe Geological Structure (Spain) for Evaluation as a Potential CO2 Storage Site

The Caspe geological structure was formed by the convergence of the Iberian Range and the Catalonian Coastal Range, during the Tertiary compression. Traditionally, the Caspe structure has been interpreted from seismic profiles without considering surface structural data. The aim of this study is to build a 3D geological model taking into account the structural data from the geological map, stress fields and lineaments, and evaluate its possibility as potential CO2 storage site. Four surfaces have been modelled: Buntsandstein Top, Muschelkalk-I Top, Muschelkalk-II Top and Cenozoic Bottom. Considering the geometry and depth for storage the target reservoir was considered to be the Buntsandstein facies. The available seismic data indicate that the Buntsandstein facies top is at approximately 500 m depth and hosts a deep saline aquifer. The target reservoir series include the conglomerate and sandstone of the Hoz del Gallo and Cañizar Fms (Buntsandstein Facies) with an average thickness of 500 m and 21% porosity. The seal comprises the shales and silts of the Röt Fm with an average thickness of 100-150 m. The structure volume was calculated based on the -500 mbsl for the Buntsandstein top deepest closed contour lines. The estimated volume is 5, 800 Mm3 with most of CO2 in gaseous state

Thermal-Aware Data Flow Analysis

This paper suggests that the thermal state of a processor can be approximated using data flow analysis. The results of this analysis can be used to evaluate the efficacy of thermal-aware compilation strategies, or as input to thermal-aware optimizations that occur in the early stages of back-end compilation. We propose different ways how the exploitation of thermal behavior knowledge can be included in the different compilation phases. Copyright 2009 ACM

Optimal Loop-Unrolling Mechanisms and Architectural Extensions for an Energy-Efficient Design of Shared Register Files in MPSoCs

In this paper we introduce a new hardware/software approach to reduce the energy of the shared register file in upcoming embedded architectures with several VLIW processors. This work includes a set of architectural extensions and special loop unrolling techniques for the compilers of MPSoC platforms. This complete hardware/software support enables reducing the energy consumed in the register file of MPSoC architectures up to a 60% without introducing performance penalties

Modeling and Dynamic Management of 3D Multicore Systems with Liquid Cooling

Three-dimensional (3D) circuits reduce communication delay in multicore SoCs, and enable efficient integration of cores, memories, sensors, and RF devices. However, vertical integration of layers exacerbates the reliability and thermal problems, and cooling efficiency becomes a limiting factor. Liquid cooling is a solution to overcome the accelerated thermal problems imposed by multi-layer architectures. In this paper, we first provide a 3D thermal simulation model including liquid cooling, supporting both fixed and variable fluid injection rates. Our model has been integrated in HotSpot to study the impact on multicore SoCs. We design and evaluate several dynamic management policies that complement liquid cooling. Our results for 3D multicore SoCs, which are based on a 3D version of UltraSPARC T1, show that thermal management approaches that combine liquid cooling with proactive task allocation are extremely effective in preventing temperature problems. Our proactive management technique provides an additional 75% average reduction in hot spots in comparison to applying only liquid cooling. Furthermore, for systems capable of varying the coolant flow rate at runtime, our feedback controller increases the improvement to 95% on average

Exploring Temperature-Aware Design of Memory Architectures in VLIW Systems

This paper presents a thermal model to analyze the temperature evolution in the shared register files found on VLIW systems. The use of this model allows the analysis of several factors that have an strong impact on the heat transfer: layout topology, placement and memory accesses. Finally, some relevant conclusions are obtained after analyzing the thermal behavior of several multimedia applications

Compilation for Delay Impact Minimization in VLIW Embedded Systems

Tomorrow’s embedded devices need to run high resolution multimedia as well as need to support multistandard wireless systems which require an enormous computational complexity with a very low energy consumption and very high performance constraints. In this context, the register file is one of the key sources of power consumption and performance bottleneck, and its inappropriate design and management can severely affect the performance of the system. In this paper, we present a new compilation approach to mitigate the performance implications of technology variation in the shared register file in upcoming embedded VLIW architectures with several processing units. The compilation approach is based on a redefined register assignment policy and a set of architectural modifications to this device. Experimental results show up to a 67% performance improvement with our technique

Variable Ratio Hydrostatic Transmission Simulator for Optimal Wind Power Drivetrains

This work presents a hydromechanical transmission coupled to an electric AC motor and DC generator to simulate a wind power turbine drive train. The goal of this project was to demonstrate and simulate the ability of a hydrostatic variable ratio system to produce constant electric power at varying wind speeds. The experimental results show that the system can maintain a constant voltage when a 40% variation in input speed is produced. An accompanying computer simulation of the system was built and experimentally validated showing a discrete error no larger than 12%. Both the simulation and the experimental results show that the electrical power output can be regulated further if an energy storage device is used to absorb voltage spikes produced by abrupt changes in wind speed or wind direction

3D Thermal-Aware Floorplanner for Many-Core Single-Chip Systems

Heat removal and power density distribution delivery have become two major reliability concerns in 3D stacked technology. In this paper, we propose a thermal-driven 3D floorplanner. Our contributions include: (1) a novel multi-objective formulation to consider the thermal and performance constraints in the optimization approach; (2) an efficient Mixed Integer Linear Programming (MILP) representation of the floorplanning model; and (3) a smooth integration of the MILP model with an accurate thermal modelling of the architecture. The experimental work is conducted for two realistic many-core single-chip architectures: an homogeneous system resembling Intel’s SCC, and an improved heterogeneous setup. The results show promising improvements of the mean, peak temperature and the thermal gradient, with a reduced overhead in the wire length of the system